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1. general description the 74abt574a high-performance bicmos dev ice combines low static and dynamic power dissipation with high sp eed and high output drive. the 74abt574a is an 8-bit, edge triggered r egister coupled to eight 3-state output buffers. the clock input (cp) and output enable input (oe ) control gates, control the two sections of the device independently. the state of each data input (dn, one set-up time before the low-to-high clock transition) is transferred to the q output of the corresponding flip-flop. when oe is low, the stored data appears at the outputs. when oe is high, the outputs are in the high-impedance ?off? state, which means they do not drive or load the bus. the 3-state output buffers are designed to drive heavily loaded 3-state buses, mos memories, or mos microprocessors. the active-low output enable (oe ) controls all eight 3-state buffers independ ent of the clock operation. 2. features and benefits ? 74abt574a is flow-through pinout version of 74abt374a ? inputs and outputs on opposite side of package allow easy interface to microprocessors ? 3-state outputs for bus interfacing ? power-on 3-state ? power-on reset ? common output enable ? latch-up protection exceeds 500 ma per jesd78b class ii level a ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v ? live insertion/extraction permitted. 74abt574a octal d-type flip-flop; 3-state rev. 2 ? 23 november 2012 product data sheet
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 2 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74ABT574AN ? 40 ? cto+85? c dip20 plastic dual in-line package; 20 leads (300 mil) sot146-1 74abt574ad ? 40 ? cto+85? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74abt574adb ? 40 ? cto+85? c ssop20 plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 74abt574apw ? 40 ? cto+85? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 fig 1. logic symbol fig 2. iec logic symbol mna798 d0 d1 d2 d3 d4 d5 d6 d7 oe cp q0 q1 q2 q3 q4 q5 q6 q7 11 1 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 mna446 12 13 14 15 16 17 18 11 c1 1 en 1d 19 9 8 7 6 5 4 3 2 fig 3. logic diagram 001aah077 d0 cp oe q0 d cp q ff1 d1 q1 d cp q ff2 d2 q2 d cp q ff3 d3 q3 d cp q ff4 d4 q4 d cp q ff5 d5 q5 d cp q ff6 d6 q6 d cp q ff7 d7 q7 d cp q ff8
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 3 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 5. pinning information 5.1 pinning 5.2 pin description fig 4. pin configuration dip20 and so20 fig 5. pin configuration ssop20 and tssop20

table 2. pin description symbol pin description oe 1 3-state output enable input (active low) d0, d1, d2, d3, d4, d5, d6, d7 2, 3, 4, 5, 6, 7, 8, 9 data input gnd 10 ground (0 v) cp 11 clock pulse input (active rising edge) q0, q1, q2, q3, q4, q5, q6, q7 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output v cc 20 supply voltage
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 4 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 6. functional description [1] h = high voltage level; h = high voltage level one setup time before the high-to-low cp transition; l = low voltage level; l = low voltage level one setup time before the high-to-low cp transition; z = high-impedance off-state; ? = low-to-high clock transition. 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] the performance capability of a high-perfo rmance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reli ability. the maximum junction temperature of this integrated circuit should not excee d 150 ? c. 8. recommended operating conditions table 3. function table [1] operating mode input internal flip-flop output oe cp dn qn load and read register l ? ll l l ? hh h load register and disable output h ? ll z h ? hh z table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v v i input voltage [1] ? 1.2 +7.0 v v o output voltage output in off-state or high-state [1] ? 0.5 +5.5 v i ik input clamping current v i < 0 v ? 18 - ma i ok output clamping current v o < 0 v ? 50 - ma i o output current output in low-state - 128 ma t j junction temperature [2] - 150 ?c t stg storage temperature ? 65 +150 ?c table 5. operating conditions voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit v cc supply voltage 4.5 - 5.5 v v i input voltage 0 - v cc v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i oh high-level output current ? 32--ma
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 5 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 9. static characteristics i ol low-level output current - - 64 ma ? t/ ? v input transition rise and fall rate 0 - 5 ns/v t amb ambient temperature in free air ? 40 - +85 ?c table 5. operating conditions ?continued voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 6. static characteristics symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c unit min typ max min max v ik input clamping voltage v cc = 4.5 v; i ik = ? 18 ma ? 1.2 ? 0.9 - ? 1.2 - v v oh high-level output voltage v i = v il or v ih v cc = 4.5 v; i oh = ? 3 ma 2.5 2.9 - 2.5 - v v cc = 5.0 v; i oh = ? 3 ma 3.0 3.4 - 3.0 - v v cc = 4.5 v; i oh = ? 32 ma 2.0 2.4 - 2.0 - v v ol low-level output voltage v cc = 4.5 v; i ol =64ma; v i =v il or v ih - 0.42 0.55 - 0.55 v v ol(pu) power-up low-level output voltage v cc = 5.5 v; i o =1ma; v i =gndor v cc [1] - 0.13 0.55 - 0.55 v i i input leakage current v cc =5.5v; v i =v cc or gnd - ? 0.01 ? 1.0 - ? 1.0 ? a i off power-off leakage current v cc = 0 v; v i or v o ? 4.5 v - ? 5.0 ? 100 - ? 100 ? a i o(pu/pd) power-up/power-down output current v cc =2.0v; v o =0.5v; v i =gndor v cc ; oe high [2] - ? 5.0 ? 50 - ? 50 ? a i oz off-state output current v cc = 5.5 v; v i = v il or v ih v o = 2.7 v - 5.0 50 - 50 ? a v o = 0.5 v ? 50 ? 5.0 - ? 50 - ? a i lo output leakage current high-state; v o =5.5v; v cc =5.5v; v i =gndor v cc -5.050 - 50 ? a i o output current v cc = 5.5 v; v o = 2.5 v [3] ? 180 ? 40 ? 180 ? 40 ma i cc supply current v cc = 5.5 v; v i = gnd or v cc outputs high-state - 100 250 - 250 ? a outputs low-state - 24 30 - 30 ma outputs disabled - 100 250 - 250 ? a ? i cc additional supply current per input pin; v cc = 5.5 v; one input at 3.4 v; other inputs at v cc or gnd [4] -0.51.5 - 1.5ma
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 6 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state [1] for valid test results, do not load data into the flip-flops (or latches) after applying the power. [2] this parameter is valid for any v cc between 0 v and 2.1 v, with a transition time of up to 10 ms. a transition time of up to 100 ? s is permitted between v cc = 2.1 v and v cc = 5 v ? 10 %. [3] do not test more than one output at a time, and the duration of the test must not exceed one second. [4] this characteristic is the increase in supply current for each input at 3.4 v. 10. dynamic characteristics c i input capacitance v i =0vor v cc -3- - -pf c o output capacitance outputs disabled; v o =0vor v cc -6- - -pf table 6. static characteristics ?continued symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c unit min typ max min max table 7. dynamic characteristics gnd = 0 v; for test circuit, see figure 9 . symbol parameter conditions 25 ?c; v cc = 5.0 v ? 40 ?c to +85 ?c; v cc =5.0 v ? 0.5 v unit min typ max min max f max maximum frequency see figure 6 150 400 - 125 - mhz t plh low to high propagation delay cp to qn, see figure 6 1.5 3.0 4.4 1.5 5.0 ns t phl high to low propagation delay cp to qn, see figure 6 2.0 3.4 4.7 2.0 5.1 ns t pzh off-state to high propagation delay oe to qn; see figure 8 1.0 2.9 4.1 1.0 5.0 ns t pzl off-state to low propagation delay oe to qn; see figure 8 2.5 3.8 5.2 2.5 5.7 ns t phz high to off-state propagation delay oe to qn; see figure 8 1.8 3.1 4.3 1.8 5.0 ns t plz low to off-state propagation delay oe to qn; see figure 8 1.4 2.6 3.8 1.4 4.0 ns t su(h) set-up time high dn to cp; see figure 7 1.0 0.6 - 1.0 - ns t su(l) set-up time low dn to cp; see figure 7 1.0 0.2 - 1.0 - ns t h(h) hold time high cp to dn; see figure 7 +1.0 ? 0.7 - 1.0 - ns t h(l) hold time low cp to dn; see figure 7 +1.0 ? 0.4 - 1.0 - ns t wh pulse width high cp; see figure 6 2.0 0.7 - 2.0 - ns t wl pulse width low cp; see figure 6 2.0 0.8 - 2.0 - ns
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 7 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 11. waveforms v m = 1.5 v v ol and v oh are typical voltage output levels that occur with the output load. fig 6. propagation delay clock input (cp) to output (qn), clock pulse (cp) width and maximum clock (cp) frequency 001aac445 cp input qn output t phl t plh t wh t wl 1 / f max v m v oh v i gnd v ol v m v m = 1.5 v the shaded areas indicate when the input is per mitted to change for predictable output performance. fig 7. set-up and hold times data output (dn) to clock (cp) 001aac738 v m cp input v m v m v m v m v m t su(h) t h(h) t su(l) t h(l) dn input v l gnd v l gnd
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 8 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state v m = 1.5 v v ol and v oh are typical voltage output levels that occur with the output load fig 8. 3-state output (qn) enable and disable times 001aac448 t pzl qn output qn output oe input v ol v oh v i v m gnd 3.5 v gnd t plz t pzh t phz v ol + 0.3 v v oh ? 0.3 v v m v m a. input pulse definition b. test circuit test data is given in table 8 . r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 9. test circuit for measuring switching times 001aai298 v m v m t w t w 10 % 90 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % 90 % 10 % 10 % t f t r t r t f v ext v cc v i v o mna616 dut c l r t r l r l g table 8. test data input load v ext v i f i t w t r , t f c l r l t phl , t plh t pzh , t phz t pzl , t plz 3.0 v 1 mhz 500 ns ? 2.5 ns 50 pf 500 ? open open 7.0 v
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 9 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 12. package outline fig 10. package outline sot146-1 (dip20) unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot146-1 99-12-27 03-02-13 a min. a max. b z max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2 4.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.078 0.17 0.02 0.13 sc-603 ms-001 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 20 1 11 10 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) (1) dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 10 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state fig 11. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 11 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state fig 12. package outline sot339-1 (ssop20) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p q (1) zywv references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 8 0 o o 0.13 1.25 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot339-1 mo-150 99-12-27 03-02-19 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 11 0 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 a max. 2
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 12 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state fig 13. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 11 0 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 13 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 13. abbreviations 14. revision history table 9. abbreviations acronym description bicmos bipolar complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model table 10. revision history document id release date data sheet status change notice supersedes 74abt574a v.2 20121123 product data sheet - 74abt574a v.1 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. 74abt574a v.1 19950522 product specification - -
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 14 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwise in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74abt574a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 november 2012 15 of 16 nxp semiconductors 74abt574a octal d-type flip -flop; 3-state export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74abt574a octal d-type flip -flop; 3-state ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 23 november 2012 document identifier: 74abt574a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 recommended operating conditions. . . . . . . . 4 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 14 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 contact information. . . . . . . . . . . . . . . . . . . . . 15 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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